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Date
Nov. 16. 2001
64M (x16) Flash Memory
LH28F640BFN-PTTLZ2
LHF64FZ2
* Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliance * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 2.41
LHF64FZ2 CONTENTS
1
PAGE 44-Lead SOP Pinout ................................................... 3 Pin Descriptions.......................................................... 4 Memory Map .............................................................. 5 Identifier Codes and OTP Address for Read Operation ............................................. 6 OTP Block Address Map for OTP Program............... 7
PAGE 1 Electrical Specifications......................................... 14 1.1 Absolute Maximum Ratings ........................... 14 1.2 Operating Conditions ...................................... 14 1.2.1 Capacitance .............................................. 15 1.2.2 AC Input/Output Test Conditions ............ 15 1.2.3 DC Characteristics ................................... 16
Bus Operation............................................................. 8 Command Definitions ................................................ 9 Functions of Block Lock and Block Lock-Down...... 11 Block Locking State Transitions upon Command Write................................................. 11 Status Register Definition......................................... 12 Extended Status Register Definition ........................ 13 1.2.4 AC Characteristics - Read-Only Operations......................... 17 1.2.5 AC Characteristics - Write Operations ................................. 20 1.2.6 Reset Operations ...................................... 22 1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance.................... 23 2 Related Document Information.............................. 24
Rev. 2.41
LHF64FZ2
2
LH28F640BFN-PTTLZ2 64Mbit (4Mbitx16) Page Mode Flash MEMORY
64M density with 16Bit I/O Interface High Performance Reads * 90/35ns 8-Word Page Mode Low Power Operation * 2.7V Read and Write Operations * Automatic Power Savings Mode Reduces ICCR in Static Mode Enhanced Code + Data Storage * 5s Typical Erase/Program Suspends OTP (One Time Program) Block * 4-Word Factory-Programmed Area * 4-Word User-Programmable Area High Performance Program with Page Buffer * 16-Word Page Buffer Operating Temperature 0C to +70C Flexible Blocking Architecture * Eight 4K-word Parameter Blocks * One-hundred and twenty-seven 32K-word Main Blocks * Top Parameter Location CMOS Process (P-type silicon substrate) Enhanced Data Protection Features * Individual Block Lock and Block Lock-Down with Zero-Latency * All blocks are locked at power-up or device reset. * Block Erase, Full Chip Erase, (Page Buffer) Word Program Lockout during Power Transitions Automated Erase/Program Algorithms * 3.0V Low-Power 11s/Word (Typ.) Programming Cross-Compatible Command Support * Basic Command Set * Common Flash Interface (CFI) Extended Cycling Capability * Minimum 100,000 Block Erase Cycles 44-Lead SOP ETOXTM* Flash Technology Not designed or rated as radiation hardened
The product, which is Page Mode Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at VCC=2.7V-3.6V. Its low voltage operation capability greatly extends battery life for portable applications. The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states. The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage. Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation.
Rev. 2.41
LHF64FZ2
3
A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 44-LEAD SOP STANDARD PINOUT 34 13.2mm x 28.2mm 33 32 TOP VIEW 31 30 29 28 27 26 25 24 23
RST# WE# A20 A21 A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
Figure 1. 44-Lead SOP Pinout
Rev. 2.41
LHF64FZ2
Table 1. Pin Descriptions Symbol A0-A21 DQ0-DQ15 Type INPUT INPUT/ OUTPUT Name and Function ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21
4
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code and identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to standby levels. RESET: When low (VIL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first). DEVICE POWER SUPPLY (2.7V-3.6V): With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins.
CE#
INPUT
RST# OE# WE# VCC GND
INPUT INPUT INPUT SUPPLY SUPPLY
Rev. 2.41
LHF64FZ2
5
BLOCK NUMBER
134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
ADDRESS RANGE
3FF000H - 3FFFFFH 3FE000H - 3FEFFFH 3FD000H - 3FDFFFH 3FC000H - 3FCFFFH 3FB000H - 3FBFFFH 3FA000H - 3FAFFFH 3F9000H - 3F9FFFH 3F8000H - 3F8FFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH
BLOCK NUMBER ADDRESS RANGE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 000000H - 007FFFH
Figure 2. Memory Map (Top Parameter)
Rev. 2.41
LHF64FZ2
6
Table 2. Identifier Codes and OTP Address for Read Operation Code Manufacturer Code Device Code Block Lock Configuration Code Manufacturer Code Top Parameter Device Code Block is Unlocked Block is Locked Block is not Locked-Down Block is Locked-Down OTP OTP Lock OTP NOTES: 1. Top parameter device has its parameter blocks at the highest address. 2. DQ15-DQ2 are reserved for future implementation. 3. OTP-LK=OTP Block Lock configuration. 4. OTP=OTP Block data. Address [A21-A0](1) 000000H 000001H Block Address +2 Block Address +2 000080H 000081000088H Data [DQ15-DQ0] 00B0H 00B0H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 OTP-LK OTP 1 2 2 2 2 3 4 Notes
Rev. 2.41
LHF64FZ2
7
[A21-A0] 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H 000080H
Reserved for Future Implementation (DQ15-DQ2)
Customer Programmable Area Lock Bit (DQ1) Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)
Rev. 2.41
LHF64FZ2
8
Table 3. Bus Operation(1, 2) Mode Read Array Output Disable Standby Reset Read Identifier Codes/OTP Read Query Write 3 6 6,7 4,5,6 Notes 6 RST# VIH VIH VIH VIL VIH VIH VIH CE# VIL VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL Address X X X X See Table 2 See Appendix X DQ0-15 DOUT High Z High Z High Z See Table 2 See Appendix DIN
NOTES: 1. See DC Characteristics for VIL or VIH voltages. 2. X can be VIL or VIH for control pins and addresses. 3. RST# at GND0.2V ensures the lowest power consumption. 4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when VCC=2.7V-3.6V. 5. Refer to Table 4 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LH28F640BF series for more information about query code.
Rev. 2.41
LHF64FZ2
9
Table 4. Command Definitions(10) Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 First Bus Cycle Notes 2 2,3,4 2,3,4 2,3,11 2 2,3,5 2,5,8 2,3,5,6 2,3,5,7 2,8 2,8 2 2,9 2 2,3,8 Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) X X X BA or WA X BA X WA WA BA or WA BA or WA BA BA BA OA Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H Write Write Write Write BA BA BA OA 01H D0H 2FH OD Write Write Write Write BA X WA WA D0H D0H WD N-1 Read Read Read IA or OA QA BA or WA ID or OD QD SRD Second Bus Cycle Oper(1) Addr(2) Data(3)
NOTES: 1. Bus operations are defined in Table 3. 2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle. X=Any valid address within the device. IA=Identifier codes address (See Table 2). QA=Query codes address. Refer to Appendix of LH28F640BF series for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See Figure 3). 3. ID=Data read from identifier codes. (See Table 2). QD=Data read from query database. Refer to Appendix of LH28F640BF series for details. SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, and the data within OTP block (See Table 2). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of LH28F640BF series for details. 8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted
Rev. 2.41
LHF64FZ2
10
while the block erase operation is being suspended. 9. Following the Clear Block Lock Bit command, the selected block is unlocked regardless of lock-down configuration. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 11. When the status register data is read, input the address to which the erase or program operation is executed.
Rev. 2.41
LHF64FZ2
11
Table 5. Functions of Block Lock(4) and Block Lock-Down Current State State [00] [01] [10] [11]
(3)
DQ1 0 0 1 1
(1)
DQ0(1) 0 1 0 1
State Name Unlocked Locked Unlocked Locked
Erase/Program Allowed (2) Yes No Yes No
NOTES: 1. DQ0=1: a block is locked; DQ0=0: a block is unlocked. DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [01] regardless of the states before power-off or reset operation. 4. OTP (One Time Program) block has the lock function which is different from those described above.
Table 6. Block Locking State Transitions upon Command Write Current State State [00] [01] [10] [11] DQ1 0 0 1 1 DQ0 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [01] No Change [11] No Change Clear Lock(1) No Change(3) [00] No Change [10] Set Lock-down(1) [11](2) [11] [11](2) No Change
NOTES: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written.
Rev. 2.41
LHF64FZ2
12
Table 7. Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 R 11 R 3 R 10 PBPSS 2 NOTES: R 9 DPS 1 R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program
Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit, attempt, an improper command sequence was entered. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status.
SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R) should be masked out when polling the status register. SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Rev. 2.41
LHF64FZ2
13
Table 8. Extended Status Register Definition R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available
NOTES: After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) register.
Rev. 2.41
LHF64FZ2 1 Electrical Specifications 1.1 Absolute Maximum Ratings*
Operating Temperature During Read, Erase and Program ...... 0C to +70C (1) Storage Temperature During under Bias............................... -10C to +80C During non Bias................................ -65C to +125C Voltage On Any Pin (except VCC)............................ -0.5V to VCC+0.5V (2) VCC Supply Voltage ........................... -0.2V to +3.9V (2) Output Short Circuit Current ........................... 100mA (3)
14
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5V which, during transitions, may overshoot to VCC +2.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time.
1.2 Operating Conditions
Parameter Operating Temperature VCC Supply Voltage Main Block Erase Cycling Parameter Block Erase Cycling Symbol TA VCC Min. 0 2.7 100,000 100,000 Typ. +25 3.0 Max. +70 3.6 Unit C V Cycles Cycles 1 Notes
NOTES: 1. See DC Characteristics tables for voltage range-specific specification.
Rev. 2.41
LHF64FZ2
15
1.2.1 Capacitance(1) (TA=+25C, f=1MHz)
Parameter Input Capacitance RST# Input Capacitance Output Capacitance NOTE: 1. Sampled, not 100% tested. Symbol CIN CIN COUT Condition VIN=0.0V VIN=0.0V VOUT=0.0V Min. Typ. 6 24 10 Max. 8 30 12 Unit pF pF pF
1.2.2 AC Input/Output Test Conditions
VCC INPUT 0.0 AC test inputs are driven at VCC(min) for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends at VCC/2. Input rise and fall times (10% to 90%) < 5ns. Worst case speed conditions are when VCC=VCC(min). VCC/2 TEST POINTS VCC/2 OUTPUT
Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 9. Configuration Capacitance Loading Value
VCC(min)/2
1N914
RL=3.3k DEVICE UNDER TEST CL Includes Jig Capacitances. CL OUT
Test Configuration VCC=2.7V-3.6V
CL (pF) 50
Figure 5. Transient Equivalent Testing Load Circuit
Rev. 2.41
LHF64FZ2 1.2.3 DC Characteristics
VCC=2.7V-3.6V Symbol ILI ILO ICCS ICCAS ICCD Parameter Input Load Current Output Leakage Current VCC Standby Current VCC Automatic Power Savings Current VCC Reset Power-Down Current Average VCC Read Current Normal Mode Average VCC Read 8 Word Read Current Page Mode VCC (Page Buffer) Program Current VCC Block Erase, Full Chip Erase Current VCC (Page Buffer) Program or Block Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC Lockout Voltage Notes 1 1 1 Min. -1.0 -1.0 6 Typ. Max. +1.0 +1.0 25 Unit A A A A A mA
16
Test Conditions VCC=VCCMax., VIN/VOUT=VCC or GND VCC=VCCMax., CE#=RST#= VCC0.2V VCC=VCCMax., CE#=GND0.2V RST#=GND0.2V VCC=VCCMax., CE#=VIL, OE#=VIH, f=5MHz
1,4 1 1
4 4 15
20 20 25
ICCR
1 1,5 1,5 1,2 5 5 5 5 3 VCC -0.2 1.5 -0.4 VCC -0.4
5 20 10 15
10 60 30 210 0.4 VCC + 0.4 0.2
mA mA mA A V V V V V
ICCW ICCE ICCWS ICCES VIL VIH VOL VOH VLKO
CE#=VIH
VCC=VCCMin., IOL=100A VCC=VCCMin., IOH=-100A
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25C unless VCC is specified. 2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VCCVLKO, and not guaranteed outside the specified voltage. 4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 5. Sampled, not 100% tested.
Rev. 2.41
LHF64FZ2 1.2.4 AC Characteristics - Read-Only Operations(1)
VCC=2.7V-3.6V, TA=0C to +70C Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH Read Cycle Time Address to Output Delay CE# to Output Delay Page Address Access Time OE# to Output Delay RST# High to Output Delay CE# or OE# to Output in High Z, Whichever Occurs First CE# to Output in Low Z OE# to Output in Low Z Output Hold from First Occurring Address, CE# or OE# change 2 2 2 2 0 0 0 3 3 Parameter Notes Min. 90 90 90 35 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns
17
NOTES: 1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. 3. OE# may be delayed up to tELQV tGLQV after the falling edge of CE# without impact to tELQV.
Rev. 2.41
LHF64FZ2
18
A21-0 (A) A20-0 (A)
VIH VIL tAVQV
VALID ADDRESS tEHQZ tGHQZ
CE# (E)
VIH VIL
tELQV
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQV tGLQX tELQX VOH VOL tPHQV tOH VALID OUTPUT
DQ15-0 (D/Q)
High Z
VIH
RST# (P)
VIL
Figure 6. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 2.41
LHF64FZ2
19
A21-3 (A) A20-3 (A)
VIH VIL tAVQV VIH VIL
VALID ADDRESS
A2-0 (A)
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
CE# (E)
VIH VIL tELQV tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQX tELQX tAPA tOH tGLQV
DQ15-0 (D/Q)
VOH VOL
High Z
tPHQV
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VIH
RST# (P)
VIL
Figure 7. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks
Rev. 2.41
LHF64FZ2 1.2.5 AC Characteristics - Write Operations(1), (2)
VCC=2.7V-3.6V, TA=0C to +70C Symbol tAVAV tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tWHGL (tEHGL) tWHR0 (tEHR0) Write Cycle Time RST# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High WE# (CE#) Pulse Width High Write Recovery before Read WE# (CE#) High to SR.7 Going "0" 3, 6 5 3 4 4 7 7 Parameter Notes Min. 90 150 0 60 40 50 0 0 0 30 30 tAVQV+ 50 Max.
20
Unit ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 7. Refer to Table 4 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.
Rev. 2.41
LHF64FZ2
21
NOTE 1 A20-0 (A) A21-0 (A)
VIH VIL
NOTE 2
VALID ADDRESS tAVAV
NOTE 3
VALID ADDRESS tAVWH (tAVEH)
NOTE 4
VALID ADDRESS
NOTE 5
CE# (E)
VIH VIL tELWL (tWLEL) tWHEH (tEHWH)
tWHAX (tEHAX)
NOTES 5, 6
tWHGL (tEHGL)
OE# (G)
VIH VIL tPHWL (tPHEL) VIH VIL tWLWH (tELEH ) tWHWL (tEHEL)
NOTES 5, 6
WE# (W)
tWHQV1,2,3 (tEHQV1,2,3) tWHDX (tEHDX) tDVWH (tDVEH)
DQ15-0 (D/Q)
VIH VIL DATA IN DATA IN VALID SRD
tWHR0 (tEHR0)
SR.7 (R)
"1" "0"
RST# (P)
VIH VIL
NOTES: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 8. AC Waveform for Write Operations
Rev. 2.41
LHF64FZ2 1.2.6 Reset Operations
tPHQV RST#
(P)
22
VIH VIL
High Z
tPLPH
VALID OUTPUT
V DQ15-0 (D/Q) OH VOL
(A) Reset during Read Array Mode
ABORT COMPLETE
SR.7="1"
tPLRH RST#
(P)
tPHQV
VIH VIL
High Z
tPLPH
VALID OUTPUT
V DQ15-0 (D/Q) OH VOL VCC(min) GND
(B) Reset during Erase or Program Mode
VCC
tVHQV t2VPH tPHQV
RST#
VIH
(P)
VIL V DQ15-0 (D/Q) OH VOL
High Z
VALID OUTPUT
(C) RST# rising timing
Figure 9. AC Waveform for Reset Operations Reset AC Specifications (VCC=2.7V-3.6V, TA=0C to +70C)
Symbol tPLPH tPLRH t2VPH tVHQV
Parameter RST# Low to Reset during Read (RST# should be low during power-up.) RST# Low to Reset during Erase or Program VCC 2.7V to RST# High VCC 2.7V to Output Delay
Notes 1, 2, 3 1, 3, 4 1, 3, 5 3
Min. 100
Max.
Unit ns
22 100 1
s ns ms
NOTES: 1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. 4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there.
Rev. 2.41
LHF64FZ2 1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
VCC=2.7V-3.6V, TA=0C to +70C Symbol Parameter 4K-Word Parameter Block Program Time 32K-Word Main Block Program Time Word Program Time OTP Program Time 4K-Word Parameter Block Erase Time 32K-Word Main Block Erase Time Full Chip Erase Time tWHRH1/ tEHRH1 tWHRH2/ tEHRH2 tERES (Page Buffer) Program Suspend Latency Time to Read Block Erase Suspend Latency Time to Read Latency Time from Block Erase Resume Command to Block Erase Suspend Command Page Buffer Command is Notes Used or not Used 2 2 2 2 2 2 2 2 2 2 4 4 5 500 Not Used Used Not Used Used Not Used Used Not Used Min. Typ.(1) Max.(2) Unit 0.05 0.03 0.38 0.24 11 7 36 0.3 0.6 80 5 5 0.3 0.12 2.4 1.0 200 100 400 4 5 700 10 20 s s s s s s s s s s s s s
23
tWPB tWMB tWHQV1/ tEHQV1 tWHOV1/ tEHOV1 tWHQV2/ tEHQV2 tWHQV3/ tEHQV3
NOTES: 1. Typical values measured at VCC=3.0V and TA=+25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1". 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished.
Rev. 2.41
LHF64FZ2 2 Related Document Information(1)
Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F640BF series Appendix
24
Rev. 2.41
i
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC(min) VCC GND VIH RP# (P) (RST#) ADDRESS (A) VIL tF VIH CE#
(E)
tVR
t2VPH
tPHQV
VIL tR or tF VIH tAVQV Valid Address tELQV
tR or tF
tR
VIL VIH WE# (W) VIL tF VIH OE#
(G)
tGLQV
tR
VIL DATA VOH VOL High Z Valid Output
(D/Q)
Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol tVR tR tF VCC Rise Time
Parameter
Notes 1 1, 2 1, 2
Min. 0.5
Max. 30000 1 1
Unit s/V s/V s/V
Input Signal Rise Time Input Signal Fall Time
NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations.
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal VIH (Min.)
Input Signal VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit
NOTE: 1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10

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